1. Field of the Invention
The instant invention relates to a novel apparatus and method for significantly increasing the reliability of fault tolerant computing devices and related apparatus. More specifically, the invention relates to an apparatus and method for monitoring the valid operation of digital circuitry. The apparatus comprises conventional voting and unanimous circuitry and additional test circuitry, the latter functions to continually check itself, the voting circuitry and the unanimous circuitry for failures.
2. Description of the Related Art
In the field of fault tolerant computing, one of the most common techniques employed for enhancing the reliability of digital computation is to triplicate those circuits which provide critical logical functions. The application of triplicated circuit outputs through a voting circuit is most often used to determine the most common of the triplicated circuit's output values. This determination is typically accomplished by determining the most common, either two or three, of the output values and passing that value as the voting circuit's output. With related art voting schemes, any one of the three triplicated circuits can fail and correct voting circuit output values will still be produced. Additional circuitry is often used with the voting circuitry to determine if the voting is unanimous, i.e., whether all three binary inputs are the same, or whether only 2 out of 3 of the triplicated circuit outputs agree. This latter condition indicates that one of the triplicated circuits has failed. This condition is typically presented to any error control logic and/or software since it represents a potentially undetectable and fatal failure condition should either of the two remaining good circuits fail.
Heretofore, one basic limitation in the use of voting circuits and unanimous circuits for enhancing the reliability of critical digital circuitry is the inability of the test circuitry to determine whether the test circuit itself has failed. In other terms, related art circuitry which provides monitoring functions are susceptible to failure and such failures represent a significant reliability factor in the failure detection technique.
The above mentioned limitation relating to single voting and unanimous circuits also extends to paralleled sets of such circuits which are used for checking the individual bits of bytes or of words. Composite error signals may then be formed from the bits thus tested. Again, any of the individual voting and unanimous circuits, including the composite error signal circuitry, may fail and go undetected.
From the foregoing, the need should be appreciated for an extremely reliable self-checking device for use in fault tolerant computing applications and more particularly a device which continually checks voting circuitry, unanimous circuitry and itself for failures. Accordingly, a fuller understanding of the invention may be obtained by referring to the SUMMARY OF THE INVENTION, and the Detailed Description of the Preferred Embodiment, in addition to the scope of the invention as defined by the claims taken in conjunction of the accompanying drawings.